Developing FPGA-accelerated cloud applications with SDAccel: Theory
Section outline
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Week 1 provides a detailed description of FPGA technologies starting from a general description down to the discussion on the low-level configuration details of these devices, to the bitstream composition and the description of the configuration registers.
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Week 2 is going to see how this language has been used in SDAccel and the main "components" of this toolchain.
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Week 3 will first understand how an FPGA is working, also from a computational point of view. We will briefly compare a processor sequential execution with the intrinsic parallel nature of an FPGA implementation.Furthermore, within this week we are going to familiarise ourselves with the application optimisation flow.
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Week 4 will provide a bird's eye view on the available SDAccel optimisations. The presented optimisations are not the only available ones, but they are more a list of recommendations to optimise the performance of an OpenCL application that have to be used as a starting point for ideas to consider or investigate further.
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Week 5 will focus on four specific optimisations: loop unrolling, loop pipelining, array partitioning optimisation and the host optimisations.
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Week 6 will introduce FPGA-augmented cloud infrastructures.
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